Integrated circuits are the weak points of today's electronic devices

Both the integration density of integrated circuits and their internal processing speed continue to rise, which also entails a higher susceptibility in terms of EMC. Fast disturbance pulses which were not even perceived by slower ICs in the past may now lead to serious trouble such as signal errors or functional faults. Immunity tests on individual IC pins show ways in which even more robust ICs can be manufactured in the future despite the increasing density of integration.

The characteristics of integrated circuits (ICs) can no longer be ignored if one wishes to ensure a high robustness of electronic devices to electromagnetic interference. Burst and ESD disturbances enter electronic devices from outside and reach the pins of ICs via conductors. Disturbances enter the ICs both through their pins and also directly via magnetic and electric disturbance fields. The effects on their function may vary considerably, from brief tolerable faults such as short-time toggling of a port's output, for example, through to the IC's total failure, i.e. a permanent loss of function.

Different immunity levels of microcontroller pins

Fig. 1 shows the immunity levels that have been determined for the individual pins of a microcontroller, a 8051 derivative in this example. A P301 high-impedance probe was used in this measurement to apply disturbance pulses of 1.5 ns (rise time) / 20 ns (tail time) which may have amplitudes between +/- 5 V and 500 V. This probe is part of the test system described in [1]. The disturbance pulses correspond to the interference to which the pins of an IC are subjected if a burst or ESD test is performed on a device while this is in operation or if the device is used in an industrial environment where interference occurs. It can be seen that the pins have very different immunity levels. The port pin inputs can be expected to always switch at approximately the same disturbance voltage. The signal that is passed on into the IC is corrupted. Any resulting signal errors are of no concern for this example in practice since port signals can be filtered correspondingly before being further processed. Pins that have an asynchronous influence on the IC, such as the reset pin 4, or pins that have a direct effect on the overall IC function, such as the quartz crystal oscillator connection XTAL1 pin 15, are an exception here. It is not common to take preventive measures such as filters or similar remedies in the IC - as is the case here too. The immunity level is around < 5 Volt and thus very low in this example.

An analysis of the port pin fault images shows that the faults do not result from signal errors that have been passed on to the core area, which should be able to be handled through appropriate software measures. Rather, these are generally serious faults that affect the entire IC with a subsequent successful restart through reset or a complete crash. This means that the disturbance that is injected into the ports affects the IC's core area.

On the trail of signal errors and functional faults

Fig. 2 shows the chain of interactions. Port interference may be caused along two lines of interaction.

1. A disturbance voltage disturbs the port and produces signal errors.
2. A disturbance current flows through the input protection diodes, Vdd and Vss system to the core area or other central functional complexes such as PLL, memory, etc. and affects these. Serious functional faults occur.

The IC's internal structure has to be taken into account for further clarification. Fig. 3 shows an equivalent circuit diagram that has been simplified specifically for this purpose.

A P300 disturbance pulse generator and a signal source are connected to the port pin of an IC. The test generator generates disturbance pulses with a rise time of 1.5 ns and a tail time of 20 ns. The disturbance pulse is injected into the port pin via 18 pF. The IC has a port area and core area that are connected internally and isolated by two diodes in this example.

Fast transient processes inside the IC cannot be measured with an oscilloscope. The interrelationships are thus simulated below.

The internal inductances (bond wires and metal surfaces) are significant in this respect, as are external backup capacitors (C3, C4) and internal backup capacitors (C1, C2) on the supply lines.

Initially, only the port area is considered. The core area is isolated and C1 is set to 1 pF.

Fig. 4 shows the results: plot 01 shows the signal from the signal source and the disturbance pulse of the test generator reduced by the factor 100. Plot 02 shows the effect of both events on the port pin. The disturbance pulse is differentiated by the coupling capacitance CP of the test generator and limited by the port's protection diodes. The limitation of the needle pulse (leading edge of the disturbance pulse) is inhibited by the inductances (L1, L2, L8 and L9) located in the Vdd and Vss branches. Voltage peaks of up to 18 V occur at the input. The port circuit, which is not shown here, converts the voltage at the input (plot 02) into a logic signal (plot 03).

Modern ICs become victims of fast disturbance pulses

Current pulses with a width of 3 ns and a peak value of 2 A flow into the Vdd and Vss network through the input protection diodes (plot 04). They generate voltages of up to 12 V at the line inductances of the Vdd and Vss network (plot 05). This means that all CMOS cells that are connected to the supply system can change their logic states. A drop of 3 V at the Vdd branch equates to a shutdown of the supply voltage for 3 ns in this case. Memory cells / registers will lose their logic content. The effect, of course, depends on the cells' inertia (inherent capacitance). Reloading and thus interference only occurs if the cells are fast enough. This is why fast disturbance pulses did not lead to interference in the past when ICs were slower. Modern ICs are affected by fast disturbance pulses and become the victim of interference.

Backup or blocking capacitors are provided to short-circuit high-frequency voltage differences between the Vdd and Vss branches. Due to the longitudinal inductances in the Vdd / Vss branches, the capacitors, however, have to be arranged inside the IC. External blocking is not effective for disturbances with fast rise times. Special CMOS cells can be used to establish the internal backup capacitance.

Fig. 4 shows the effect of the Vdd / Vss system's internal blocking with varying capacitance values. The effects of the disturbance pulses are represented in a stretched form.

Useful interference suppression measures

One important finding of this investigation is that apart from direct voltage dips, the disturbance pulse triggers transients that generate a differential voltage between Vdd and Vss and simply switch the IC off. The required backup capacitor value is between 1 and 10 nF. As the integration of capacitance into the IC entails additional costs, the necessary value should be determined by simulation. Attempts began around 2005 to integrate additional blocking capacitors of several nF into ICs.

But this does not completely solve the IC's interference problem. In Fig. 5, plot 09, the Vdd and Vss voltages are raised in common mode by 3.1 Volt. These common mode pulses represent the difference between the two areas if the port area, Fig. 2, is connected to the core area. This may lead to interference with the signal connections. This fault principle can also become effective between other areas that are supplied separately, such as PLLs, quartz crystal oscillators or memory components.

The entire circuit, Fig. 2, was activated for plot 10, Fig. 6. The port area with C1 = 1 pF was not blocked at all and the core area with C2 = 10 nF was blocked well. This corresponds to practical set-ups. Differential voltages of more than 3 Volt occur between the supply lines of the two areas. These differential voltages may interfere with the signal connections that are located between the two areas. The differential voltage is reduced if the port area is also blocked with 10 nF. This requires additional capacitance that is not economically feasible for an IC. A better solution is to reduce the longitudinal inductances L1 to L4 of the internal Vdd / Vss system as this allows the external backup capacitors to become effective. Low-impedance and flat supply systems are part of an interference suppression strategy that was introduced at the board level with great success around 1995. Fig. 7 shows the result if this strategy is applied to ICs. The effect is clear: there is no longer a voltage dip between Vss1 and Vss2. Only the bulk resistance of the diodes that are used in the simulation still generates a voltage drop of around 1 V between Vdd1 and Vdd2. Practically speaking, this means that the Vdd / Vss systems are intermeshed. A separate metal layer would have to be included in both Vdd and Vss in the IC's die.

Change from star-type to meshed ground systems

The metal layers would have to consist of closely meshed line networks or a consistent metal surface to achieve the respective low impedance values. This, however, contradicts conventional IC design that has been based on star-type internal supply networks with a high longitudinal inductance. The supply islands were only connected on the board. As a result, the ICs immunity to interference was insufficient. This led to extra development work for the user as well as additional costs in conjunction with interference suppression on electronic modules. Traditionalists stuck to the star-type internal wiring approach.

When the change-over from star-type to meshed ground systems or flat ground system began on the board level in the mid-1990s, this approach came up against considerable resistance among specialists who believed in the traditional star-type systems. Ultimately, they were convinced by its success. Nevertheless, the change-over has taken several years and is still not complete in most companies.

Only now is the time ripe for such a change-over in the field of ICs.

Important insights will lead to more robust ICs in the future

The method of IC immunity examination on the pin level provides a number of insights that will lead to more robust ICs in the future despite an increasing density of integration and associated higher susceptibility.

• Steep-edged disturbance currents flow into the Vdd / Vss network via protection diodes
• These cause voltage dips in the Vdd / Vss system.
• Transient processes may be triggered in the Vdd / Vss system depending on internal inductances and capacitances that can be implemented.
• This results in inductance-related longitudinal voltage dips in the Vdd / Vss system and voltage differences between isolated areas.
• Internal capacitances of appropriate magnitude help minimise these processes.
• Meshing the supply systems on an IC level is expedient in this respect.